The present disclosure relates to a semiconductor device and a method for fabricating the same, and particularly to a semiconductor device including a metal insulator semiconductor field effect transistor (MISFET) having a gate electrode made of a metal material and a method for fabricating the same.
As semiconductor integrated circuit devices have become higher in the degree of integration and operating speed, the miniaturization of MISFETs has been promoted. Instead of conventional gate insulating films formed of silicon dioxide films (or silicon oxynitride films), gate insulating films made of high dielectric materials represented by alumina (Al2O3), hafnia (HfO2), and hafnium silicate (HfSiOx) have been actively studied for the practical application thereof. Because such a high dielectric film has an extremely high dielectric constant compared with that of a silicon dioxide film, it is possible to increase the thickness of a physical film, and avoid the problem of increased gate leakage current resulting from the thinning of a gate insulating film formed of a silicon dioxide film. However, when a polysilicon film is used for a gate electrode formed on a gate insulating film formed of such a high dielectric film, particularly in a p-type MISFET (hereinafter referred to as a “p-type MIS transistor”), a phenomenon called Fermi level pinning (see, e.g., C. Hobbs et al., “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, VLSI Tech. Digest 2003) causes a shift in threshold voltage, which results in the problem of degraded device performance. Accordingly, a high dielectric film can be used as a gate insulating film forming an n-type MISFET (hereinafter referred to as an n-type MIS transistor), but cannot be used as a gate insulating film forming a p-type MISFET. To avoid the problem described above, when a high dielectric film is used as a gate insulating film in a conventional semiconductor device (see, e.g., T. Hayashi et al., “Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS”, IEDM Tech. Digest 2006), a metal gate electrode made of a metal material is used for the gate electrode of a p-type MIS transistor, while a polysilicon film is used for the gate electrode of an n-type MISFET, thereby avoiding the Fermi level pinning in the p-type MIS transistor. Here, it is desirable that the gate electrode of the n-type MIS transistor has a work function of not less than 4.05 eV and not more than 4.6 eV, and the gate electrode of the p-type MIS transistor has a work function of not less than 4.6 eV and not more than 5.15 eV.
To provide the gate electrode of a p-type MIS transistor with a work function of not less than 4.6 eV and not more than 5.15 eV when, e.g., titanium nitride is used as the metal material of the gate electrode, it is necessary to inhibit the diffusion of silicon from a polysilicon film formed on the titanium nitride (see, e.g., S. Sakashita et al., “Diffusion control technique in TiN stacked metal gate electrodes for p-MISFETs”, Ext. Abst. SSDM 2006). As a method for inhibiting the diffusion of silicon, there has been known a method which increases the thickness of a physical film of a gate metal material (a single-layer structure or a laminated structure of different metal materials), a method which increases the density of (densifies) a film of a gate metal material, or the like.
A method for fabricating a conventional semiconductor device will be described below with reference to FIGS. 8A-8C. FIGS. 8A-8C are cross-sectional views showing the principal portion of the conventional semiconductor device in the gate length direction thereof in the order of the process steps of the fabrication method therefor. In each of the drawings, a left-hand region is an n-type MIS formation region 10N where an n-type MIS transistor is to be formed, and a right-hand region is a p-type MIS formation region 10P where a p-type MIS transistor is to be formed.
As shown in FIG. 8A, an isolation region 101 is selectively formed in an upper portion of a semiconductor substrate 100. As a result, a first active region 100a surrounded by the isolation region 101 is formed in the n-type MIS formation region 10N, while a second active region 100b surrounded by the isolation region 101 is formed in the p-type MIS formation region 10P. Then, a p-type well region 102a is formed in the semiconductor substrate 100 in the n-type MIS formation region 10N, while an n-type well region 102b is formed in the semiconductor substrate 100 in the p-type MIS formation region 10P.
Subsequently, over the semiconductor substrate 100, a gate-insulating-film forming film 103, and a metal film 104 made of a gate electrode material for the p-type MIS transistor are successively deposited, and then a resist mask 105 covering the p-type MIS formation region 10P, and having an opening corresponding to the n-type MIS formation region ION is formed on the metal film 104 by a photolithographic process.
Next, as shown in FIG. 8B, the metal film 104 formed on the gate-insulating-film forming film 103 in the n-type MIS formation region 10N is removed by a wet etching process using the resist mask 105. Subsequently, the resist mask 105 is removed, and then a silicon film 106 formed of, e.g., a polysilicon film having a thickness of 100 nm is deposited by, e.g., a CVD process on the gate-insulating-film forming film 103 in the n-type MIS formation region 10N and on the metal film 104 in the p-type MIS formation region 10P.
Next, as shown in FIG. 8C, a resist (not shown) having a gate pattern configuration is formed on the silicon film 106 by a photolithographic process. Thereafter, using the resist as a mask, the silicon film 106, the metal film 104, and the gate-insulating-film forming film 103 are successively patterned by a dry etching process. As a result, a first gate insulating film 103a and a first silicon film 106a are successively formed over the first active region 100a, while a second gate insulating film 103b, a second metal film 104b, and a second silicon film 106b are successively formed over the second active region 100b. 
In this manner, a first-gate-electrode forming portion 106A having the first gate insulating film 103a and the first silicon film 106a is formed over the first active region 100a, while a second-gate-electrode forming portion 106B having the second gate insulating film 103b, the second metal film 104b, and the second silicon film 106b is formed over the second active region 100b. 